Architecture and Protocol for Optical Packet Switching

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Architecture and Protocol for Optical Packet Switching

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Title: Architecture and Protocol for Optical Packet Switching
Author: Condiff, Lesley Rolf
Abstract: This dissertation proposes a number of single and parallel processor architectures and protocols for optical packet switching in all optical networks making use of a number of recent advances in high speed processors and optical buffers and a number of packet contention resolution techniques in wavelength, time, and space, alternative routing and processing speeds. The input and output lines can transmit multiple wavelengths per line (i.e., wavelength division multiplexed lines). In the developed architectures the header of a packet is separated from the body and is processed for determining the route and wavelength to be used to transmit the packet. The body is delayed for as long as is needed for processing the header. Thus only a portion and not the whole packet need to be saved. This reduces buffer size requirement. The optical packet switch also utilizes dynamically updated Link & Channel Availability Tables and dynamically updated hierarchical Routing Tables (OSPF, Next Best Route). Thirteen different Single Input Processor architectures and the Parallel Input Processor architectures are developed and evaluated with and without packet contention resolution techniques. Parallel processors are used at the output in all architectures except one. The various architectures are simulated by using OPNET software simulation package and their performance is evaluated from these simulation results in terms of packet loss rate, average throughput per line and total throughput. Many of the architectures did not provide acceptable performance. The Parallel Input Processor architecture with the number of wavelength converters equal to the number of input channels and Parallel Input Processor with Next Best Route are shown to provide the best performance (nearly zero packet loss) when using 10 gigabit per second processors for 10 gigabit per second input line rates. Higher rate input lines can be accommodated by down multiplexing the incoming data into 10 gigabit streams and parallel processing these streams. These results are presented on graphical forms. The results of this dissertation will lead to implementation of optical packet switching with its resultant benefits to the all optical networking.
Description: Degree awarded: Ph.D. Electrical Engineering and Computer Science. The Catholic University of America
Date: 2011-06-24

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